The present invention relates to a semiconductor memory device. More particularly, the present invention is applicable to a semiconductor memory device having a write assist circuit and to a semiconductor device including such a semiconductor memory device.
Some semiconductor devices include a volatile semiconductor memory device such as a static random access memory (SRAM). For SRAMs generated by a miniaturized semiconductor process, a negative-bias write assist technology is proposed (refer to U.S. Pat. Nos. 7,379,347 and 7,952,911). In order to secure a write margin, the negative-bias write assist technology drives one line of a bit line pair to a negative bias not higher than a ground potential (0 V) during a write operation. The negative-bias write assist technology improves the drive capability of a select transistor coupled to a selection-level word line and a negatively-biased bit line. Therefore, even if a memory cell is formed of a miniaturized transistor, its write margin can be adequately secured by the negative-bias write assist technology.